A High Resolution Digital-To-Analog Converter For The PET
G. Eric Matthews and
Pamela L. Carter
Department of Physics
Wake Forest University
Winston-Salem, NC
It is relatively simple to interface a microprocessor compatible digital-to-analog converter (D/A) to the Commodore PET. For most applications, an 8 bit signal is adequate. An 8 bit D/A interface can be implemented easily via the User Port. However, in many applications a very accurate voltage is necessary, and an 8 bit signal may be inadequate. A 12 bit signal has 16 times the resolution of an 8 bit signal and therefore allows much finer control over the output voltage. Connecting a 12 bit interface to the User Port can be somewhat complicated since the computer only offers 8 data lines there. However, the PET has a Memory Expansion Port (located on the right side of the cabinet) that includes fully buffered, partially decoded address lines [Ref. 1]. Use of the expansion port offers the additional advantage of allowing multiple interfaces to be connected and used at once merely by assigning each a unique address. The interface described here utilizes the signals available at this port.
Since the computer has only an 8 bit data bus, interfacing a 12 bit D/A is more difficult than implementing an 8 bit device. This can be accomplished through double buffered data latching. A latch holds the signal until the program signals the latch to accept a new value and to pass it on to the next part of the circuit. Signalling the latch to hold or pass data is accomplished from BASIC through POKE commands. The actual interfacing technique follows.
The Hardware
The first step in the design of an analog output port is to determine the accuracy of the conversion that is to be performed. If the desired analog accuracy is ± 1 %, or 1 part in 100, then a 7 bit conversion is adequate, with a resolution of better than 1/2% (one part in 64). ± 0.1% accuracy requires 10 bits to be within the desired range. When the accuracy level has been determined, the digital-to-analog converter chip (DAC) can be chosen. The characteristics of the DAC should meet the requirements of the circuit in which it is to be used. In this interface an Analog Devices AD7541 (CMOS 12-Bit Monolithic Multiplying DAC) was chosen [Ref. 2].
The next step is to determine the addresses to be devoted to receiving the data for the latches. Checking the computer memory to find available space is necessary in order to avoid interfering with other operations of the computer. The most straightforward way of passing a 12 bit number to the DAC is by assigning one address to the upper eight bits of the DAC and assigning a second address to the lower four bits of the DAC. Therefore at least two addresses must be devoted to the interface. For simplicity, only partial decoding of the address bus (the high order eight bits) has been used. The addresses chosen are $90XX and $91XX (where an X means "don't care"). These two addresses do not conflict with the Toolkit or Wordpro. A POKE to $90XX enables a latch for the upper eight bits and a POKE to $91XX enables the corresponding latch for the lower four bits.
A schematic diagram of the circuit employed is shown in figure 1. The chip used for address decoding is the 74154 (4 Line Decoder) [Ref. 3]. This chip decodes four binary-coded inputs to one of 16 mutually exclusive outputs when each of the two strobe inputs are low. Address decoding with the PET is simplified by the availability of partially decoded address lines on the Memory Expansion Port: SEL9 is low when the high order four bits of the address bus corresponds to $9. Applied to the strobe inputs of the 74154 are SEL9 and A1 1 for the chosen address. To the four binary-coded inputs A,B,C,D are fed the 02 clock, A8,A9,A10 respectively. As configured, output 1 will be low if and only if the 02 clock is high, SEL9 is low, and A8-11 are low (as during a POKE to $90XX). Out-put 3 will be low when the 02 clock is high, SEL9 is low, A8 is high, and A9-11 are low as during a POKE to $91XX). These two outputs provide the enabling pulses for the latches. Note that this circuit does not decode the R/W line. Care should be taken, therefore, that no PEEKs to the above addresses be included in any program using this circuit as this would result in spurious data being passed to the DAC.
The latches used here are 7475 Quad Latches [Ref. 4] and function as temporary storage for binary information. Information at the data inputs is transferred to the outputs when the enable is high. Therefore the two independent (low) output pulses from the 74154 must be inverted before being applied to the 7475 enable pins. These two inverted pulses correspond to the enabling addressed $90XX and $91XX. The output of the latch follows the input as long as the enable is high. When the enable goes high the output is held constant no matter the state of the input until the enable goes high again. The purpose in double buffering the data latches is to pass all 12 data bits at the same instant to the DAC. If the latches were only single buffered, then the eight bit data latch (two 7475's) and the four bit data latch (one 7475) would be enabled with separate POKE commands, and an instant of time would exist when the data input to the DAC is in an intermediate state between the previous input and the present input. The data in this state is erroneous and produces a glitch in the voltage output. Double buffering avoids this glitch by passing the data to the DAC in the following way.
Address $90XX enables the first eight bit latch. This passes the eight most significant bits to the first latch. Then POKEing address $91XX enables the four bit latch simultaneously with the second eight bit latch. This enable passes the four least significant bits to the tour bit latch and transfers the eight upper bits from the first latch to the second. Therefore all 12 data bits appear at the inputs of the DAC at the same time producing a smooth transition of voltage [Ref. 5].
The AD7541 consists of an R-2R ladder and 12 CMOS current switches which perform the D/A conversion. Adding a 741 operational amplifier at Iout I and connecting the output of the 741 to RFeedback completed this simple, but very powerful, circuit.
The Software
I he following program allows the input of any number from 0 to 4095. The D/A outputs the corresponding voltage from 0 to 11.25 volts.
100 INPUT "V 110 U = INT(V/16) : REM-UPPER 8 BITS 120 L = V-16 * U : REM-LOWER 4 BITS 130 POKE 36864, U : REM-HIGH 8 BITS GO TO $90XX 140 POKE37120, L : REM-LOW4 BITS GO TO $91XX 150 GOTO 100
Additional Comments
After construction of the D/A interface, it was seen that double buffering the lower four bits rather than the upper eight bits of the data for the DAC would require one less chip and also would allow, the use of the interface as an eight bit D/A. For use as an eight bit D/A, a POKE command at the beginning of the program would set the lower four bits to 0 and then a single POKE would output the data to the upper eight bits.
Figure 1. Digital-to-Analog Converter
Some difficulty has been encountered in finding connectors compatible to the PET Memory Expansion Port. The authors prefer the Relia-Tac connectors (Amphenol 221-1660 receptacle strips with 220-502 contacts) for this purpose.
The only modification required to use this circuit with other 6502 based machines is a change of the address decoder. Partially decoded address lines are not universally available, so one may need to use an additional 74154 to decode the high order four bits of the address bus. If the addresses $90XX and $91XX are occupied in your machine, you will need to change the decoder to an unused address.
It should be emphasized that the decision to decode eight address lines was rather arbitrary. The authors chose that figure because it is the maximum that could be decoded with a single 74154.
Finally, note that if you wish to implement additional analog outputs, more address decoders are unnecessary. Outputs 5, 7, 9, etc. of the 74154 as configured correspond to addresses $92XX, $93XX, $94XX, etc.
A high resolution analog output is straightforward to implement for the PET microcomputer. The circuit is easy to construct using readily available components. Using the Memory Expansion Port rather than the User Port allows one to add other analog outputs by merely changing the address assigned to the interface. The potential uses of the interface are restricted only by the imgination of the designer. For example, the availability of two analog outputs allows high resolution plotting via an X-Y recorder.
This circuit also demonstrates the ease with which the Memory Expansion Port can be utilized for interfacing. We share with Marvin L. Dejong the hope that there are other "hardware nuts" out there interested in such circuits.
References:
1. CBM Professional Computer User Manual, Commodore Business Machines, Inc., Santa Clara, June 1979, pp. 82–83.
2. Analog Devices Spec Sheet for AD7541 CMOS 12-Bit Monolithic Multiplying DAC.
3. Signetics Data Book, Signetics Corporation, 1974, pp. 2–144–145.
4. Signetics Data Book, Signetics Corporation, 1974, pp. 2–76–77.
5. Short, Kenneth L., Microprocessors and Programmed Logic, Prentice-Hall, Inc., Englewood Cliffs, 1981, pp. 403–312.